1. Field of the Invention:
The present invention relates to a data processing device which has a plurality of working registers, and, in particular, to a data processing device which employs a stored program method.
2. Description of the Related Art:
A data processing device having a plurality of general registers called working registers can be characterized by the number of register operands which one instruction can designate. For instance, in a conventional RISC architecture, three registers can be designated with a typical operation instruction. Two of them are used as a source register for supplying two values to be added in an addition instruction, and the other one is used as a destination register for storing the operation result. This method is referred to as a "three register operand" method.
As an example of this method, the format of an instruction for operation among registers according to an MIPS architecture is shown in FIG. 1. The MIPS architecture is disclosed in "A quantative approach for design, realization and evaluation of a computer architecture" by David A. Patterson, John L. Hennessy (published by Nikkei BP in December 1992). In the MIPS architecture, machine code is of a 32-bit fixed length, and an instruction for operation among registers consists of the following fields: (from the MSB side) an instruction operation code 201 for indicating the type of instruction; a first source register number 202 for indicating a register which contains a first source operand; a second source register number 203 for indicating a register which contains a second source operand; a destination register number 204 for indicating a register which stores an operation result; a short constant 205 for indicating a small constant needed by some instructions; and an extension instruction operation code 206 that is an extension of an instruction operation code needed by some instructions. Note that bracketed numbers following respective field names in the drawing indicate the number of bits constituting respective fields.
As another example of the prior art, Cold RISC architecture has recently been made available. The Cold RISC architecture uses a shorter instruction achieved by reducing the code size of a basic instruction to thereby compress a program area. As a design example of such an architecture is Hitachi single-chip RISC microcomputer SH 7000 series, the format of an instruction for operation among registers used therein is shown in FIG. 2. In the SH7000 architecture, machine code is of a 16-bit fixed length, and an instruction for operation among registers consists of the following fields: (from the MSB side) a first instruction operation code 301 for indicating the type of instruction; a source register number 302 for indicating a register which contains a second source operand used in an operation; a destination register number 303 for indicating a register which stores an operation result, and contains a first source operand used in an operation; and a second instruction operation code 304 for indicating, in cooperation with the first instruction operation code, the type of instruction.
This method is significantly different from the above MIPS architecture in that one of the source operands needed in a binomial operation is extracted from the destination register. This method is referred to as a binomial register operand method.
A recently available processor employs a method to process instructions by overlapping them like a pipeline architecture, an adaptable construction thereof being shown in FIG. 3.
In the drawing, an instruction fetch section 401 receives the next instruction to be executed from an instruction cache 406 and outputs the obtained machine code to an instruction decode section 402. The instruction will be processed through the following procedure.
The instruction decode section 402 first separates the machine code into fields according to the type of instruction, and then extracts the following: an instruction operation code 411 for indicating the type of an operation to be processed, the immediate data 412 that is a constant operand embedded in the machine code, a first source register number 413, a second source register number 414, and a destination register number 415. Then, data of the registers in a register file 403 designated by the first and second source register numbers are read.
When the instruction operation code instructs execution of an operation such as an addition or subtraction operation, an operation execution section 404 executes the instructed operation according to the content read from source registers, so that the operation result 419 is stored in the register designated by the destination register number.
When the instruction operation code instructs storage in a memory, the operation execution section 404 computes a data memory address 416, so that data is written into a data cache 407 using the data memory address and write data 417.
When the instruction operation code instructs load from a memory, data is read from the data cache using the data memory address 416 generated by the operation execution section 404, so that the read data 419 is written into the register designated by the destination register number.
If the instruction cache or the data cache does not have a target machine code or data, machine code or data is transmitted from an external memory to the cache via an external memory interface 408.
The three register operand method is characterized in that it requires fewer execution instructions compared to the two register operand method. This is because an operation result always overwrites a source operand stored in one of the registers in the two register operand method. If data stored in a register is referred to by a plurality of instructions, the data may have to be copied to another register before executing operations. Taking as an example a function which executes a binomial operation using registers rs1 and rs2, and stores the operation result in a register rd will be described. In the case of the three register operand method, this function can be executed through one instruction, whereas it cannot using the two register operand method. In order to execute this function in the two register operand method, two instructions are necessary, namely, 1) an instruction for copying data in a register rs1 into a register rd, and 2) an instruction for executing a binomial operation op, for data in the registers rd and rs2 and storing the operation result in the register rd.
As described above, the three register operand method is effective in reducing the number of instructions, that is, the number of cycles to execute a program. However, this conventional method involves many problems in view of reduction of a program size because it causes a longer instruction length for each individual instruction.
Meanwhile, in the Cold RISC architecture, wherein a 16-bit machine code, for instance, is employed as a reference instruction to thereby reduce a program size, it is difficult to designate three registers as operands with a only single 16-bit instruction. In the case where sixteen general registers are provided, for instance, a 12-bit field is necessary to designate three registers as operands, which leaves only a 4-bit field available. However, it is difficult to store encoded data regarding the type of instruction or operation in the 4-bit field.